I’m lumping the MOSFET and BJT labs together for an interesting reason. Normally, the process for making these two devices is pretty different. While both will have an N, P, and another N region (for N-MOSFETs and NPN BJTs), MOSFETS usually have these three regions as adjacent rectangular areas, while BJTs have them as three concurrent cuboid regions.
However, we (or rather, our lab manual) screwed up. The process for making a MOSFET actually had us adding, then removing, the gate oxide. What this meant is we had direct contact to the N, P, and N regions – a very weak BJT.
Half of us ended up continuing with that, and half of us hadn’t etched the gate oxide, so were able to modify the process to create a MOSFET. Because both processes started from the same place, I’m going to include both in this lab.
Introduction
This lab creates both a MOS Field Effect Transistor (MOSFET) and a bi-junction transistor (BJT). The MOSFET is a device where the gate voltage with respect to the source pin voltage determines the drain-source conductance. The BJT is a device where the base-emitter voltage determines the collector current (it just so happens by coincidence that the base current is proportional to the collector current).
This lab utilizes techniques from the MOSCAP lab and the PN diode lab to produce three adjacent rectangular regions of N, P, and N-type silicon. For the BJT, contacts are created directly to these three regions via aluminum deposition, whereas for the MOSFET, a gate oxide is created before adding the contacts.
Procedure and Results
MOSFET/BJT Base
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Obtain a non-epitaxial P-type silicon chip.
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Place the chips in a boat and oxide etch.
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Rinse with acetone/IPA and air-blow-dry.
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Place the chips in a field oxide furnace at $1100^oC$ for 30 minutes.
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Gas should be flowing through the water flask. The water should be hot.
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Remove the chips and place them on an aluminum block to cool.
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Spin photoresist onto the chips.
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Apply the source/drain mask.
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Turn on the UV to expose the mask.
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Develop the photoresist.
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After developing, masked regions are clearly visible.
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Etch the oxide region for 4 minutes away from the soruce/drain regions.
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Rinse with acetone and IPA to remove any remaining photoresist.
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Etched chip. lighter regions are exposed silicon next to the darker oxide regions.
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Place the chips in a boron furnace at $950^oC$ for 30 minutes to dope the source/drain regions N-type.
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Spin more photoresist onto the chips.
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Chip with a thin layer of photoresist.
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Find a good source/drain region on the chip.
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Position the gate mask over the center of the source/drain regions/
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After exposing the photoresist and developing it, apply another oxide etch for 4 minutes.
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Rinse with acetone/IPA to remove leftover photoresist.
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Grow the gate oxide region at $1000^oC$ (first at $1 ft^3/hr O_2$ for 30 minutes, then $N_2$ for 10 minutes.
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Remove the chips and place them on an aluminum block to cool.
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Spin more photoresist, and…
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…bake the chips.
Completing the MOSFET
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Apply the contact (aluminum deposition) mask.
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UV expose for 1.5 minutes.
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Develop the photoresist.
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Place the chips (photoresist-down) onto the aluminum deposition chamber grate. Run the machine to apply a thin aluminum contact.
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Gently remove the photoresist in acetone to get rid of unwanted aluminum, leaving aluminum in just the contact areas.
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Place the chip in the analyzer and place probes onto the three contact regions of the MOSFET.
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Running the analyzer shows a characteristic MOSFET $I_D$ vs $V_{DS}$ curve.
Completing the BJT
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Apply the contact mask.
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UV-expose the photoresist.
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Chip after exposure.
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Develop the photoresist.
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Oxide etch away the gate oxide we’d added earlier (woops).
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Prepare the aluminum deposition chamber.
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Place the chips, photoresist-down onto the grate.
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Bring the vacuum down…
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…and engage the fine vacuum pump, then run a current through the titanium wire to vaporize the aluminum.
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Remove non-contact aluminum by gently swirling the chip in acetone.
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Metalized chip.
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Place the chip on the analyzer.
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Apply probes to the three regions – base, collector, emitter. In this device, the collector and base regions may have had slight contact due to mask misalignment.
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Running the analyzer shoes curves characteristic of a diode-connected transistor where the collector and base are connected together.